Title :
Improved structure for efficient charge recovery logic
Author :
Liu, F. ; Lau, K.T.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fDate :
9/3/1998 12:00:00 AM
Abstract :
An improved structure for efficient charge recovery logic (IECRL) with better power performance than ECRL coupled with an improved output waveform is presented. At 25 MHz and Vdd=5 V, the power dissipation of IECRL is ~60% that of the ECRL circuit. HSPICE simulations also show that the voltage can be scaled down to 1.5 V Vdd and that the power saving is further improved. At 25 MHz and Vdd=1.5 V, the power dissipation of the IECRL circuit is ~49% that of the ECRL circuit
Keywords :
CMOS logic circuits; logic design; 1.5 to 5 V; 25 MHz; HSPICE simulation; charge recovery logic; power dissipation reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19981210
