Low Noise 64-Channel ASIC for AC and DC Coupled Strip Detectors

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 μV/e^- to 50 μV/e^- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e^- for a peaking time T_p=115 ns and C_det=1.2 pF. With a DC-coupled CdTe detector, the ENC is 210 e^- rms for a peaking time T_p=380 ns and C_det=2 pF and the leakage current Idleak=0.15 nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e^- rms (at one sigma level). The ASIC is designed in a CMOS 0.35 μm technology and its total area is 4800×5000 μm².