Title :
Reconfigurable phase-locked loops on FPGA utilising intrinsic synchronisability
Author :
Tanaka, H. ; Hasegawa, A. ; Haruyama, S.
Author_Institution :
Comput. Sci. Lab., Sony Corp., Tokyo, Japan
fDate :
1/18/2001 12:00:00 AM
Abstract :
A new digital phase-locked loop (PLL), utilising the intrinsic synchronisability of electrical oscillators, on a field-programmable gate array has been developed. By interconnecting such PLLs, a dynamically reconfigurable clock network was formed. This has previously been difficult with conventional PLL techniques
Keywords :
clocks; digital phase locked loops; field programmable gate arrays; synchronisation; FPGA; digital phase-locked loop; dynamically reconfigurable clock network; electrical oscillators; intrinsic synchronisability; reconfigurable phase-locked loops;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010051
