Title :
Efficient parallel time-slot interchanger for high-performance SDH/SONET digital crossconnect systems
Author_Institution :
NTT Network Innovation Labs., Yokosuka, Japan
fDate :
1/18/2001 12:00:00 AM
Abstract :
A parallel design of time-slot interchangers is refined in order to scale the interchangers´ capacity in an efficient manner. Performance analysis shows that this design scheme requires significantly less memory compared with a conventional parallel design because of newly implemented load-balancing switches, while keeping its switching control complexity to a minimum
Keywords :
SONET; packet switching; synchronous digital hierarchy; SDH/SONET digital crossconnect systems; design scheme; load-balancing switches; parallel time-slot interchanger; switching control complexity;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010079
