DocumentCode
1429748
Title
Efficient parallel time-slot interchanger for high-performance SDH/SONET digital crossconnect systems
Author
Obara, H.
Author_Institution
NTT Network Innovation Labs., Yokosuka, Japan
Volume
37
Issue
2
fYear
2001
fDate
1/18/2001 12:00:00 AM
Firstpage
81
Lastpage
83
Abstract
A parallel design of time-slot interchangers is refined in order to scale the interchangers´ capacity in an efficient manner. Performance analysis shows that this design scheme requires significantly less memory compared with a conventional parallel design because of newly implemented load-balancing switches, while keeping its switching control complexity to a minimum
Keywords
SONET; packet switching; synchronous digital hierarchy; SDH/SONET digital crossconnect systems; design scheme; load-balancing switches; parallel time-slot interchanger; switching control complexity;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010079
Filename
898269
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