Title :
Robust Two-Phase RZ Asynchronous SoC Interconnects
Author :
Elrabaa, Muhammad E S
Author_Institution :
Comput. Eng. Dept., KFUPM, Dhahran, Saudi Arabia
fDate :
6/1/2011 12:00:00 AM
Abstract :
A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE simulations with a 0.13 μm, 1.2 V technology and compared to that of the best-in-class asynchronous transceivers in terms of forward and backward latencies, throughput, energy per bit transfer and design complexity. Results demonstrate the superior overall performance of the new transceiver.
Keywords :
asynchronous circuits; integrated circuit interconnections; protocols; system-on-chip; SPICE simulations; asynchronous transceivers; delay-insensitive asynchronous handshaking protocol; design complexity; dual-rail circuit implementation; on-chip communication; size 0.13 mum; two-phase RZ asynchronous SoC interconnects; voltage 1.2 V; Delay; Integrated circuit interconnections; Latches; Network-on-a-chip; Pipeline processing; Protocols; Robustness; Throughput; Timing; Transceivers; Asynchronous interconnects; CMOS digital integrated circuits; networks-on-chip (NoC); systems-on-chip (SoC);
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2042240
