Design of a one-transistor-cell multiple-valued CAM

Author

Hanyu, Takahiro ; Kanagawa, Naoki ; Kameyama, Michitaka

Author_Institution

Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1669

Lastpage

1674

Abstract

A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-μm standard EEPROM technology

Keywords

CMOS memory circuits; content-addressable storage; 0.8 micron; 10.7 ns; content-addressable memory; floating-gate MOS transistor; four-valued CAM; high-density CAM; highly parallel search operations; multiple-valued CAM; multiple-valued data representation; one-transistor-cell configuration; threshold voltage; CADCAM; Circuits; Computer aided manufacturing; EPROM; Intelligent systems; Logic; MOSFETs; Nonvolatile memory; Random access memory; Threshold voltage; Vehicle dynamics;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542311

Filename

542311