A 64-b quad-issue CMOS RISC microprocessor

Author

Gaddis, Neela ; Lotz, Jonathan

Author_Institution

Hewlett-Packard Co., Palo Alto, CA, USA

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1697

Lastpage

1702

Abstract

The HP-PA8000 is a 180-MHz quad-issue custom VLSI implementation of the HP-PA 2.0 64-b architecture delivering 11.84 SPECint95 and 20.18 SPECfp95 with 3.8 million transistors integrated on a 17.68 mm×19.1 mm die in a 3.3-V, 0.5-μm CMOS process. Specialized clock circuits and extensive use of dynamic logic are key factors in this microprocessor´s performance. Attention to clock analysis and distribution resulted in a 170 ps clock skew between any two clock nodes. This microprocessor utilizes a 56-entry instruction reorder buffer (IRE), register renaming, and dual functional units to fully exploit instruction level parallelism

Keywords

CMOS digital integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; timing; 0.5 micron; 180 MHz; 3.3 V; 64 bit; CMOS RISC microprocessor; HP-PA architecture; HP-PA8000; clock circuits; clock distribution; custom VLSI implementation; dual functional units; dynamic logic; instruction level parallelism; instruction reorder buffer; quad-issue microprocessor; register renaming; Adders; CMOS logic circuits; CMOS process; Circuits; Clocks; Delay; Hardware; Laboratories; Logic; Logic circuits; Microprocessors; Out of order; Reduced instruction set computing; Registers; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542314

Filename

542314