A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation

Author

Von Kaenel, Vincent ; Aebischer, Daniel ; Piguet, Christian ; Dijkstra, Evert

Author_Institution

Swiss Center for Electron. & Microtechnol. Inc., Neuchatel, Switzerland

Volume

31

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

1715

Lastpage

1722

Abstract

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100

Keywords

CMOS digital integrated circuits; digital phase locked loops; jitter; microprocessor chips; synchronisation; timing circuits; 0.35 micron; 1 to 1.35 V; 1.2 to 1.5 mW; 176 to 574 MHz; 320 MHz; CMOS PLL; jitter; low-power clock generator; microprocessor clock generation; phase-locked loop; triple-metal CMOS process; CMOS process; Clocks; Energy consumption; Frequency; Jitter; Microprocessors; Phase locked loops; Time measurement; Voltage; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1996.542316

Filename

542316