Design of large high-speed binary multiplier units

An attempt has been made to review the methods of multiplication available for use in a large high-speed computing machine. Number lengths of 50 to 60 bits and multiplicatiion times of less than 0.5 ¿s were the design aims. Suitable multiplier units will make use of carry-save adders to reduce the time for each addition cycle, and will decode several multiplier bits in each cycle to reduce the number of cycles required. The number of carry-save adders to be used is set largely by economic considerations. The number of multiplier bits to be decoded in each cycle is determined by the time required to form multiples of the multiplicand prior to cycling. It is shown that the best compromise between cost and speed is achieved if two or three carry-save adders are used in a serial-parallel configuration, and three or two multiplier bits are decoded in each cycle, respectively. A comparison with several other multipliers is made. A method for incorporating carry assimilation at the less significant end of the product is described, thus requiring the final propagate addition to be only single length, while still retaining the full double-length result. An indication of the effect of number length on the conclusions is inclued, but is not worked out in complete detail.