Title :
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
Author :
Kuroda, Tadahiro ; Fujita, Tetsuya ; Mita, Shinji ; Nagamatsu, Tetsu ; Yoshioka, Shinichi ; Suzuki, Kojiro ; Sano, Fumihiko ; Norishima, Masayuki ; Murota, Masayuki ; Kako, Makoto ; Kinugawa, Masaaki ; Kakumu, Masakazu ; Sakurai, Takayasu
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
fDate :
11/1/1996 12:00:00 AM
Abstract :
A 4 mm2, two-dimensional (2-D) 8×8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V DD-Vth design space is also studied
Keywords :
CMOS digital integrated circuits; data compression; digital signal processing chips; discrete cosine transforms; high definition television; video coding; 0.3 micron; 0.9 V; 10 mW; 150 MHz; CMOS triple-well double-metal technology; HDTV resolution; power dissipation; two-dimensional discrete cosine transform core processor; variable threshold-voltage scheme; video compression; video decompression; CMOS process; CMOS technology; Circuits; Degradation; Discrete cosine transforms; Fluctuations; Power dissipation; Power supplies; Threshold voltage; Two dimensional displays; Video compression;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1996.542322
