A digital error-averaging technique for pipelined A/D conversion

Capacitor mismatch is the main source of nonlinearity for pipelined analog-to-digital (A/D) converters. Here a digital error-averaging technique is presented to greatly reduce this effect. Compared to the conventional circuit, the new approach requires only one extra digital addition. This allows a very simple and compact implementation. On the other hand, the conversion speed is halved because one conversion now requires two clock cycles instead of one. Therefore this technique is most suitable when moderately high speed combined with high resolution is required