DocumentCode :
1431460
Title :
A 0.18 
CMOS Self-Mixing Frequency Tripler
Author :
Lo, Yu-Tsung ; Kiang, Jean-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
22
Issue :
2
fYear :
2012
Firstpage :
79
Lastpage :
81
Abstract :
A self-mixing frequency tripler with fundamental frequency between 6-7.3 GHz is built by cascading a doubler and a single-balanced mixer. The doubler and the mixer share a transconducting inductor to reduce the tripler core size when fabricated using the TSMC 0.18 μm RF mixed signal 1P6M process. When the input signal frequency is 6.5 GHz at the power level of 3 dBm, the measured conversion gain is - 9.5 dB, the HRR1 is 21.5 dBc, the HRR2 is 29 dBc, and the total dc power consumption is 18.8 mW.
Keywords :
CMOS integrated circuits; frequency multipliers; inductors; mixers (circuits); power consumption; CMOS; RF mixed signal; TSMC; frequency 6 GHz to 7.3 GHz; power 18.8 mW; power consumption; self-mixing frequency tripler; single-balanced mixer; size 0.18 mum; transconducting inductor; CMOS integrated circuits; Frequency measurement; Gain; Harmonic analysis; Mixers; Phase noise; Doubler; frequency tripler; harmonic generation; self-mixing; single-balanced mixer;
fLanguage :
English
Journal_Title :
Microwave and Wireless Components Letters, IEEE
Publisher :
ieee
ISSN :
1531-1309
Type :
jour
DOI :
10.1109/LMWC.2011.2180370
Filename :
6138877
Link To Document :
