A Compact Analytic Model of the Strain Field Induced by Through Silicon Vias

Author

Jan, Sun-Rong ; Chou, Tien-Pei ; Yeh, Che-Yu ; Liu, Chee Wee ; Goldstein, Robert V. ; Gorodtsov, Valentin A. ; Shushpannikov, Pavel S.

Author_Institution

Dept. of Electr. Eng. & Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

777

Lastpage

782

Abstract

The thermoelastic strains are induced by through silicon vias due to the difference of thermal expansion coefficients between the copper ( ~ 18 ppm / °C) and silicon ( ~ 2.8 ppm /°C) when the structures are exposed to a thermal ramp in the process flow. A compact analytic model (Bessel function) of the strain field is obtained using Kane-Mindlin theory, and has a good agreement with the finite-element simulations. The elastic strains in the silicon in the radial direction and angular direction are tensile and compressive, respectively. The linear superposition of the analytic model of a single via can be used in the multi-via configuration. Due to the interaction of vias, the slightly larger errors of strain occur between the two close vias when the linear superposition is used.

Keywords

finite element analysis; integrated circuit modelling; thermal expansion; thermoelasticity; three-dimensional integrated circuits; Kane-Mindlin theory; elastic strains; finite-element simulations; linear superposition; strain field compact analytic model; thermal expansion coefficients; thermal ramp; thermoelastic strains; through silicon vias; Analytical models; Iron; Semiconductor device modeling; Silicon; Solid modeling; Strain; Through-silicon vias; Compact modeling; strain field; through silicon via (TSV);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2180534

Filename

6138907