Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform

In this paper the author presents a proposed architecture (PA) for the direct two-dimensional discrete wavelet transform (DWT), which performs a complete dyadic (i.e., nonstandard) decomposition of an N₀×N₀ image in approximately N₀ ²/4 clock cycles (ccs). Therefore, it consistently speeds up the performance of other known architectures, which commonly need approximately N₀² ccs. Also, it has an AT² complexity, which is notably lower than that of other devices based on the “direct approach.” This result has been achieved by means of carefully balanced pipelining and has two “faces.” First, PA can be employed for performing processing four times faster than allowed by other architectures working at the same clock frequency (high-speed utilization), Second, it can be employed even using a four times lower clock frequency but reaching the same performance as other architectures, This second possibility allows one to reduce the supply voltage and the power dissipation respectively by four and by 16 with respect to other architectures (low-power utilization)