Dynamic gate-level body biasing for subthreshold digital design

Dynamic gate-level body biasing has been recently proposed as an alternative design methodology for subthreshold logic gates. According to this approach, a simple body biasing circuit, embedded in the logic gate, is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. This allows fast gate switching, while maintaining high energy efficiency. In this work, the proposed technique is exploited to design a low voltage mirror full-adder. When implemented in a 45 nm commercial technology, the designed circuit is 2 and 1.3 times faster than its standard CMOS and DTMOS counterparts. This is achieved while maintaining the lowest total energy per operation consumption and robustness against temperature and process variations.