A power management system architecture for LF passive RFID tags

This paper describes the architecture of a Power Management system for low-frequency passive RFID tags in a standard CMOS 0.18um technology. Passive tags have no internal power source but use the incoming RF energy transmitted by a reader to power all the circuitry inside them via a rectifier. Due to the wide variation of the rectified voltage, two stages of regulation are required: a shunt regulator working as limiter (3V) at the rectifier output, and a LDO regulator at a tighter range of 1.2V. Besides that, two blocks monitor the available RF power at the LDO regulated output and flag when the power is low for different tag operation modes: Power-on Reset (POR) during a read event, and Power Flag during a write event. All blocks rely on a low power current and voltage reference circuit. The resistor-less 5nA current reference makes use of the Self Cascode MOSFET (SCM) structure. The complete PM system is functional with 2uA current.