Title :
Leakage Characterization of 10T SRAM Cell
Author :
Islam, A. ; Hasan, M.
Author_Institution :
Dept. of ECE, BIT, Ranchi, India
fDate :
3/1/2012 12:00:00 AM
Abstract :
This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.
Keywords :
SRAM chips; buffer storage; low-power electronics; 10T SRAM cell; Schmitt trigger based SRAM cells; leakage characterization; low power dissipation; read buffers; read static noise margin; series-connected tail transistor; stacking effect; Computer architecture; Delay; Leakage current; Microprocessors; Random access memory; Threshold voltage; Transistors; Read static noise margin (RSNM); SRAM; standby power; variability;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2181387
