Comparing high-performance cells in CMOS bulk and FinFET technologies

Author

Meinhardt, Cristina ; Reis, R.

Author_Institution

Inst. de Inf.-PPGC/PGMICRO, Univ. Fed. do Rio Grande do Sul-UFRGS, Porto Alegre, Brazil

fYear

2014

fDate

25-28 Feb. 2014

Firstpage

1

Lastpage

4

Abstract

Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.

Keywords

CMOS integrated circuits; MOSFET; circuit optimisation; integrated circuit layout; invertors; logic gates; CMOS bulk technology; FinFET technology; NAND2 gates; NOR2 gates; basic cells candidates; circuit power; complex design rules; delay optimization flow; dynamic power; high performance cell library; integrated circuits design; inverters; parameter variation; regular layout synthesis flow; size 32 nm; static power; technology evolution; CMOS integrated circuits; CMOS technology; Delays; FinFETs; Inverters; Layout; Logic gates; CMOS; FinFET; microelectronics; performance; process variability;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on

Conference_Location

Santiago

Print_ISBN

978-1-4799-2506-3

Type

conf

DOI

10.1109/LASCAS.2014.6820310

Filename

6820310