DocumentCode
1433123
Title
Cellular logic array for redundant binary division
Author
Socenean¿¿u, A. ; Toma, C.I.
Author_Institution
Polytechnic Institute of Timi¿oara, Department of Computer Science, Timisoara, Romania
Volume
119
Issue
10
fYear
1972
fDate
10/1/1972 12:00:00 AM
Firstpage
1452
Lastpage
1456
Abstract
The logic cellular array of a division device that is based on the SRT division algorithm extended to the case of redundant representation of the partial remainders is reported. In the paper, redundant binary representation of the partial remainders is due to the fact that any digit can have the following values: minus one (1), zero (0) and plus one (1). Comparison of the logic array proposed with other cellular logic arrays reported in the literature for binary division yielded that, with the former design, greater operating speeds may be attained.
Keywords
cellular arrays; digital integrated circuits; dividing circuits; integrated circuits; logic circuits; redundancy; SRT division algorithm; logic cellular array; partial remainders; redundant binary division;
fLanguage
English
Journal_Title
Electrical Engineers, Proceedings of the Institution of
Publisher
iet
ISSN
0020-3270
Type
jour
DOI
10.1049/piee.1972.0287
Filename
5251594
Link To Document