• DocumentCode
    1433604
  • Title

    A CMP Model Including Global Distribution of Pressure

  • Author

    Bott, Sascha ; Rzehak, Roland ; Vasilev, Boris ; Kücher, Peter ; Bartha, Johann W.

  • Author_Institution
    Fraunhofer Center of Nanoelectronic Technol., Dresden, Germany
  • Volume
    24
  • Issue
    2
  • fYear
    2011
  • fDate
    5/1/2011 12:00:00 AM
  • Firstpage
    304
  • Lastpage
    314
  • Abstract
    In this paper, we consider the chemical-mechanical planarization (CMP) of adjacent line-space structures with different pattern density. Such structures are used on test-chips for process characterization and provide similar features like typical DRAM layouts. The predictions of previous chip-scale models based on a local balance of forces for this case are scrutinized and it is found that the distribution of the applied pressure between the different density regions is not treated sufficiently accurate in these models. We propose a simple way to include the global force balance and show that the resulting model is able to capture behavior which is more in line with general expectations for the time-evolution of typical CMP processes. The model is calibrated with data obtained for a set of test-structures with varying density and found to give a better match compared to the models described above. Especially, the prediction of the total indicated range, which is a measure for the global planarity after CMP is improved. Additionally, a parametric study shows that qualitatively different removal rate diagrams that confirm engineering experience can be obtained with the new model.
  • Keywords
    DRAM chips; chemical mechanical polishing; integrated circuit modelling; integrated circuit testing; CMP model; DRAM layouts; adjacent line-space structures; applied pressure distribution; chemical-mechanical planarization; chip-scale models; global force balance; pattern density; test-chips; test-structures; Force; Integrated circuit modeling; Layout; Mathematical model; Planarization; Predictive models; Semiconductor device modeling; Chemical–mechanical planarization (CMP); chip-scale; interaction; modeling; simulation;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2011.2107532
  • Filename
    5699407