Title :
A 14-bit 10-μs subranging A/D converter with S/H
Author :
Fernandes, John ; Lewis, Stephen R. ; Mallinson, A. Martin ; Miller, Gerald A.
Author_Institution :
Analog Devices Semicond., Wilmington, MA, USA
fDate :
12/1/1988 12:00:00 AM
Abstract :
A microprocessor-compatible, 14-bit, 10-μs subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated
Keywords :
analogue-digital conversion; error correction; sample and hold circuits; 10 mus; 14 bit; analogue error correction; conversion speed; digital error correction; five-cycle subranging flash technique; redundant bit currents; residue signal path; sample/hold amplifier; Analog-digital conversion; Clocks; Digital signal processors; Distributed amplifiers; Error correction; Linearity; Photonic band gap; Redundancy; Signal design; Signal resolution;
Journal_Title :
Solid-State Circuits, IEEE Journal of
