Title :
New dynamic flip-flops for high-speed dual-modulus prescaler
Author :
Yang, Ching-Yuan ; Dehng, Guang-Kaai ; Hsu, June-Ming ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
10/1/1998 12:00:00 AM
Abstract :
A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D flip-flops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. Also it is suitable for realizing high-speed synchronous counters. A divide-by-128/129 and 64/65 dual-modulus prescaler using the proposed flip-flops is measured in 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.8 GHz
Keywords :
CMOS logic circuits; flip-flops; pipeline processing; prescalers; 0.8 micron; 1.8 GHz; CMOS technology; D flip-flops; capacitive load reduction; dynamic flip-flops; fast pipeline technique; high-speed dual-modulus prescaler; high-speed synchronous counters; single-phase edge-triggered flip-flops; CMOS logic circuits; CMOS technology; Clocks; Counting circuits; Delay; Flip-flops; Frequency conversion; Frequency measurement; Logic circuits; Pipelines;
Journal_Title :
Solid-State Circuits, IEEE Journal of
