Title :
A 723-MHz 17.2-mW CMOS programmable counter
Author :
Chang, Hun-Hsien ; Wu, Jiin-Chuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
10/1/1998 12:00:00 AM
Abstract :
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed. Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which is 2.2 times higher than that of a conventional programmable counter. The new programmable counter was implemented in a 0.8-μm CMOS technology. The active die area is 480×100 μm. The counter was measured to operate at 723 MHz with 5 V power supply and dissipates 17.12 mW
Keywords :
CMOS logic circuits; counting circuits; flip-flops; frequency dividers; logic design; programmable logic devices; 0.8 micron; 17.12 to 17.2 mW; 5 V; 581 to 723 MHz; CMOS programmable counter; divide-by-N frequency divider; end-of-count detecting/reloading algorithm; high-speed operation; reloading delay distribution; CMOS technology; Clocks; Counting circuits; Delay; Detectors; Event detection; Flip-flops; Frequency conversion; Frequency synthesizers; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
