Title :
Performance and Vdd scaling in deep submicrometer CMOS
Author :
Chen, Kai ; Hu, Chenming
Author_Institution :
R&D Center, IBM Corp., Hopewell Junction, NY, USA
fDate :
10/1/1998 12:00:00 AM
Abstract :
Analytical models on metal-oxide-semiconductor field-effect transistor (MOSFET) scaling and complementary (CMOS) ring oscillator performance developed recently are applied to revisit CMOS design guidelines because those based on the basic long channel model are obsolete. Handy and empirical equations for deep submicrometer MOSFET drain saturation current are developed. The differences between the basic long channel model and the accurate deep submicrometer MOSFET current model are highlighted. Design guidelines on Vth and V dd scaling as well as interconnect loading effects based on the accurate models are presented
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit modelling; semiconductor device models; CMOS design guidelines; CMOS ring oscillator performance; MOSFET drain saturation current equations; deep submicron CMOS; deep submicron MOSFET current model; interconnect loading effects; long channel model; threshold voltage scaling; CMOS technology; FETs; Guidelines; Integrated circuit interconnections; MOSFET circuits; Power supplies; Predictive models; Propagation delay; Semiconductor device modeling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
