Title :
Double-edge-triggered D-flip-flops for high-speed CMOS circuits
Author :
Afghahi, M. ; Yuan, J.
Author_Institution :
LSI Design Center, Linkoping Univ., Sweden
fDate :
8/1/1991 12:00:00 AM
Abstract :
Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology
Keywords :
CMOS integrated circuits; flip-flops; integrated logic circuits; 2 micron; 320 to 400 MHz; D-flip-flops; HCMOS; double edge-triggered; high-speed CMOS circuits; power dissipation; Clocks; Delay; Digital systems; Flip-flops; Latches; Power dissipation; Pulse circuits; Repeaters; Timing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
