DocumentCode :
1434227
Title :
Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- 
Dielectrics
Author :
Gilmer, David C. ; Schaeffer, Jamie K. ; Taylor, W.J. ; Capasso, C. ; Junker, Kurt ; Hildreth, Jill ; Tekleab, Daniel ; Winstead, Brian ; Samavedam, S.B.
Author_Institution :
Austin Silicon Technol. Solutions, Freescale Semicond., Inc., Austin, TX, USA
Volume :
57
Issue :
4
fYear :
2010
fDate :
4/1/2010 12:00:00 AM
Firstpage :
898
Lastpage :
904
Abstract :
Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si1 - x Gex thicknesses, boron counterdopings, and gate work functions.
Keywords :
Ge-Si alloys; MOS integrated circuits; boron; B; band-edge PMOS threshold voltages; boron counterdopings; device simulations; dielectrics; gate work functions; gate-first complimentary metal oxide semiconductor process integration; gate-first integration technology; metal gates; metal-gate electrodes; p-channel metal oxide semiconductor threshold voltages; Boron; CMOS technology; Electrodes; FETs; Germanium silicon alloys; High-K gate dielectrics; Integrated circuit technology; MOS devices; Silicon germanium; Threshold voltage; Band-edge; PMOS; SiGe; high-$k$
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2010.2041866
Filename :
5427049
Link To Document :
