• DocumentCode
    1434318
  • Title

    Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

  • Author

    Sarpeshkar, Rahul ; Wyatt, John L., Jr. ; Lu, Nicky C. ; Gerber, Porter D.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
  • Volume
    26
  • Issue
    10
  • fYear
    1991
  • fDate
    10/1/1991 12:00:00 AM
  • Firstpage
    1413
  • Lastpage
    1422
  • Abstract
    Derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic-RAMs (DRAMs), to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into the DRAM sensing operation. The authors derive a sensitivity formula for this sensing scheme, using perturbation theory. The perturbation approach is rigorous: it avoids most approximations and ad-hoc assumptions, it introduces no free constants to be determined from simulations, and it yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design
  • Keywords
    CMOS integrated circuits; DRAM chips; perturbation theory; sensitivity analysis; bit-line load capacitance mismatch; dynamic-RAMs; explicit closed-form solution; parasitic capacitance mismatch; perturbation theory; sensitivity formula; threshold voltage mismatch; transconductance mismatch; vertically matched CMOS sense amplifier; Closed-form solution; Differential amplifiers; Fabrication; Latches; MOS devices; Parasitic capacitance; Random access memory; Signal restoration; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.90096
  • Filename
    90096