A reconfigurable wafer-scale memory

Describes the design and experimental results of a wafer-scale reconfigurable static memory. To achieve this, elementary memory chips are implemented on a 4-in wafer with a regular layout allowing step-and-repeat manufacturing, and the final memory is constructed with the good chips. After an external test, a cartography of good chips is established. Two algorithms, one based on distance sorting and the other one on a linear scanning of the wafer, have been developed to define an optimized global architecture with the good chips. Hard configuration of these chips is done by laser techniques. The switching technology to discard faulty elements and replace them by spares and the copper tracks to drive a large amount of current on typical 10-cm lines are described