Title :
A 512 16-b bit-serial sorter chip
Author_Institution :
LSI Design Center, Linkoping Univ., Sweden
fDate :
10/1/1991 12:00:00 AM
Abstract :
A hardware algorithm is presented for sorting. This algorithm is based on a highly pipelined bit-serial architecture. The processing time of this sorter is linearly proportional to the number of data. Sorting cells are much smaller and simpler than previously reported sorter cells. A single chip sorting 512 16-b keys was designed with a 2-μm process and simulated at 240 MHz. For sorting sequences up to 512 keys along, the performance of this sorter is more than 60 times better than previously reported hardware sorters
Keywords :
VLSI; microprocessor chips; parallel architectures; pipeline processing; sorting; 2 micron; VLSI; bit-serial sorter chip; hardware algorithm; highly pipelined bit-serial architecture; processing time; sorting; sorting sequences; Circuits; Clocks; Costs; Engines; Hardware; Multiplexing; Parallel algorithms; Shift registers; Sorting; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
