• DocumentCode
    1434557
  • Title

    Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

  • Author

    Hsu, Heng-Ming ; Huang, Jhao-Siang ; Chen, Szu-Yuan ; Lai, Szu-Han

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
  • Volume
    58
  • Issue
    4
  • fYear
    2010
  • fDate
    4/1/2010 12:00:00 AM
  • Firstpage
    814
  • Lastpage
    819
  • Abstract
    This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-??m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and ??0.5?? with a chip outer dimension of 100 ??m .
  • Keywords
    CMOS integrated circuits; baluns; CMOS technology; coil windings; metal layers; minimal amplitude imbalance; on-chip balun; phase imbalance; size 0.13 mum; symmetric stack layout; Balun; couple line; imbalance; on-chip;
  • fLanguage
    English
  • Journal_Title
    Microwave Theory and Techniques, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9480
  • Type

    jour

  • DOI
    10.1109/TMTT.2010.2041590
  • Filename
    5427098
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1434557