Synthesis of threshold-logic networks using Karnaugh-mapping techniques

The potential future use of threshold-logic gates as an alternative to Boolean gates depends on the ability to synthetise given Boolean problems in an economical threshold-gate form. Mapping techniques for the engineering of threshold-logic networks are presented in the paper, based on the property that all linearly separable (threshold) functions are characterised by particular patterns when plotted on Karnaugh-map layouts. The canonic characteristic-vector, or Chow-parameter, tabulations are used to derive and catalogue the map patterns that are allowable. The advantage of this approach is that a visual buildup of the synthesis is maintained, thus enabling both completely and incompletely specified networks to be handled. Threshold gates of specific capabilities, as well as universal gates, may be incorporated in the procedures.