Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width (W_NW) down to 10 nm. We found that the parasitic resistance (R_SD) of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance (C_para) increases by spacer thinning, C_para increase is much smaller than R_SD reduction, and great performance improvement is obtained for a W_NW of less than 15 nm.