A 12-bit, 200MS/s digitally calibrated pipeline ADC with Embedded Sample and Hold

Author

Abdelhamid, Mohamed R. ; Megawer, Karim M. ; Hussien, Faisal A. ; Aboudina, Mohamed M.

Author_Institution

Electron. & Electr. Commun. Eng., Cairo Univ., Cairo, Egypt

fYear

2014

fDate

13-16 April 2014

Firstpage

267

Lastpage

280

Abstract

This paper introduces a 12-bit pipeline Analog to Digital Converter (ADC) using 1.2V and 0.13μm CMOS technology. The first stage utilizes the Embedded Sample and Hold technique to eliminate the dedicated power hungry Sample and Hold circuit. Low gain Opamps are used with a Foreground Digital Calibration scheme to account for the Opamp´s finite gain and non-linearity. The ADC consumes 65 mW and achieves a maximum SNDR of 68.5 dB with an SFDR up to 80 dB which corresponds to a Figure of Merit (FOM) of about 160 fJ/step.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; operational amplifiers; sample and hold circuits; CMOS; digitally calibrated pipeline ADC; embedded sample and hold; finite gain; foreground digital calibration scheme; low gain opamps; nonlinearity; pipeline analog to digital converter; power 65 mW; size 0.13 mum; voltage 1.2 V; word length 12 bit; CMOS integrated circuits; Calibration; Capacitors; Clocks; Gain; Linearity; Pipelines; Adaptive Filter; Analog to Digital Converters; Digital Calibration; Embedded Sample and Hold; Least Mean Squares (LMS); Pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Mediterranean Electrotechnical Conference (MELECON), 2014 17th IEEE

Conference_Location

Beirut

Type

conf

DOI

10.1109/MELCON.2014.6820546

Filename

6820546