Hardware/software co-design in extensible processing platforms for combinatorial search algorithms

The paper analyzes combinatorial search algorithms over discrete matrices for which deep parallelization is strongly required and argues that the best results can be achieved with rational distribution of algorithmic operations between software and hardware. Since extensible processing platforms combine a high-performance processing system and reconfigurable logic on the same microchip, they are chosen for design space exploration and evaluation of different types of software/hardware partitioning. It is shown that reconfigurable logic is more preferable for concurrent execution of lower level application-specific operations over vectors such as Hamming weight computation, test for orthogonality/intersection, and the majority of bitwise operations. Higher level procedures mainly involving sequential processing of matrices are more efficient for implementation in software running on embedded processor. Two problems from the scope of the Boolean satisfiability were taken as a case study. All the proposed solutions were modeled in software and then were implemented, tested, and evaluated in Zynq xc7z020 microchip.