Title :
CMOS buffer tapering with interconnect capacitances
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
10/10/1996 12:00:00 AM
Abstract :
The author presents equations for optimal tapering, derived for CMOS buffers, which take account of the interconnect capacitance between stages. These equations extend existing results to the design of signal distribution networks
Keywords :
CMOS integrated circuits; buffer circuits; capacitance; delays; integrated circuit design; integrated circuit interconnections; CMOS buffer tapering; interconnect capacitances; optimal tapering; signal distribution networks;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961312
