DocumentCode
1436831
Title
CMOS buffer tapering with interconnect capacitances
Author
Blair, G.M.
Author_Institution
Dept. of Electr. Eng., Edinburgh Univ., UK
Volume
32
Issue
21
fYear
1996
fDate
10/10/1996 12:00:00 AM
Firstpage
1984
Lastpage
1985
Abstract
The author presents equations for optimal tapering, derived for CMOS buffers, which take account of the interconnect capacitance between stages. These equations extend existing results to the design of signal distribution networks
Keywords
CMOS integrated circuits; buffer circuits; capacitance; delays; integrated circuit design; integrated circuit interconnections; CMOS buffer tapering; interconnect capacitances; optimal tapering; signal distribution networks;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19961312
Filename
542881
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