Title :
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
Author :
Dai, Ke-Ren ; Liu, Wen-Hao ; Li, Yih-Lang
Author_Institution :
Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
3/1/2012 12:00:00 AM
Abstract :
The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wirelength estimations to a placer. This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and reassignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wirelength at a 1.05 × and 18.47 × faster routing speed. Moreover, the proposed layer assignment achieves fewer vias and shorter wirelength than congestion-constrained layer assignment (COLA).
Keywords :
dynamic programming; integrated circuit design; integrated circuit interconnections; minimisation; network routing; three-dimensional integrated circuits; 3D global routing; ISPD 2008 Routing Contest; NCTU-GR; circular fixed-ordering monotonic routing; congestion relaxation; congestion-constrained layer assignment; congestion-relaxed layer assignment; dynamic programming-based layer assignment; evolution-based rip-up; high-performance congestion-driven 2D global router; high-routability results; interconnection designs; layer shifting; rapid search paths; routing speed; routing techniques; simulated evolution-based rerouting; two-stage cost function; via-minimization methods; wirelength estimations; Adaptation model; Cost function; Estimation; History; Routing; Runtime; Wires; Algorithms; design automation; optimization; routing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2102780