Analysis and design of CMOS Manchester adders with variable carry-skip

Author

Chan, Pak K. ; Schlag, Martine D F

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

Volume

39

Issue

8

fYear

1990

fDate

8/1/1990 12:00:00 AM

Firstpage

983

Lastpage

992

Abstract

Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with variable carry-skip. An analysis shows that the carry-skip delay in a Manchester adder block is linearly proportional to the block size. The approach provides a general paradigm for analysis and design, applicable to different models of ripple-propagation and carry skip

Keywords

CMOS integrated circuits; adders; algorithm theory; digital arithmetic; integrated logic circuits; logic design; CMOS circuits; Manchester carry-skip adder; RC timing model; carry-skip delay; interconnect; latency; linearly proportional; one-level manchester adder; optimal block sizes; polynomial algorithms; ripple-propagation; variable carry-skip; Adders; CMOS logic circuits; Circuit analysis; Circuit synthesis; Integrated circuit interconnections; Polynomials; Propagation delay; Semiconductor device modeling; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.57038

Filename

57038