DocumentCode :
1437879
Title :
A new framework for designing and analyzing BIST techniques and zero aliasing compression
Author :
Pradhan, Dhiraj K. ; Gupta, Sandeep K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
40
Issue :
6
fYear :
1991
fDate :
6/1/1991 12:00:00 AM
Firstpage :
743
Lastpage :
763
Abstract :
A general framework for shift register-based signature analysis is presented, and a mathematical model for this framework-based on coding theory-is developed. There are two key features of this formulation, first, it allows for uniform treatment of LFSR, MISR, and multiple MISR-based signature analyzer. In addition, using this formulation, a new compression scheme for multiple output CUT is proposed. This scheme, referred to as multiinput LFSR, has the potential to achieve better aliasing than other schemes such as the multiple MISR scheme of comparable hardware complexity. Several results on aliasing are presented, and certain known results are shown to be direct consequences of the formulation. Also developed are error models that take into account the circuit topology and the effect of faults at the outputs. Using these models, exact closed-form expressions for aliasing probability are developed. A closed-form aliasing expression for MISR under an independent error model is provided
Keywords :
built-in self test; logic testing; BIST techniques; LFSR; MISR; circuit topology; coding theory; error models; exact closed-form expressions; framework; hardware complexity; mathematical model; shift register-based signature analysis; zero aliasing compression; Built-in self-test; Circuit faults; Circuit topology; Codes; Computer errors; DH-HEMTs; Hardware; Mathematical model; Shift registers; Testing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.90252
Filename :
90252
Link To Document :
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