Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Author

Kim, Keunwoo ; Fossum, Jerry G.

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA

Volume

48

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

294

Lastpage

299

Abstract

Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n⁺ and p⁺ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less

Keywords

CMOS integrated circuits; MOSFET; integrated circuit modelling; semiconductor device models; 50 nm; analytical characterizations; asymmetrical double-gate CMOS; asymmetrical double-gate MOSFETs; asymmetrical-gate devices; double-gate CMOS devices; n⁺ polysilicon gates; numerical device-simulation; optimal design; p⁺ polysilicon gates; symmetrical-gate devices; threshold-voltage control; Back; CMOS technology; Circuit simulation; Current supplies; Integrated circuit technology; Integrated circuit yield; Low voltage; MOSFETs; Medical simulation; Semiconductor films;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.902730

Filename

902730