Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET

Author

Cheng, Zhi-Yuan ; Ling, C.H.

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore

Volume

48

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

388

Lastpage

391

Abstract

A gate-channel capacitance minimum occurs in the capacitance-voltage (C-V) curve of a fully-depleted SOI MOSFET, when the front silicon surface is biased into accumulation while the back surface is maintained in strong inversion. This observation is explained in terms of a model based on the depletion width of the silicon film, taking into account the small accumulation and inversion layer thickness. A simple method is proposed to determine the flat-band potential in the SOI MOSFET

Keywords

MOSFET; accumulation layers; capacitance; electric potential; inversion layers; semiconductor device models; silicon-on-insulator; C-V curve; Si; Si-SiO₂; accumulation; accumulation layer thickness; back surface; depletion width; flat-band potential; front silicon surface biasing; fully-depleted SOI MOSFET; gate-channel capacitance characteristics; gate-channel capacitance minimum; inversion layer thickness; model; strong inversion; Capacitance measurement; Capacitance-voltage characteristics; Doping; Electrodes; MOS capacitors; MOSFET circuits; Semiconductor films; Silicon; Steady-state; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.902743

Filename

902743