Design and optimization of CMOS RF power amplifiers

Author

Gupta, Ravi ; Ballweber, Brian M. ; Allstot, David J.

Author_Institution

Maxim Integrated Products, Sunnyvale, CA, USA

Volume

36

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

166

Lastpage

175

Abstract

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; circuit CAD; circuit optimisation; differential amplifiers; inductors; integrated circuit design; integrated circuit modelling; simulated annealing; 0.6 micron; 3 V; 55 percent; 85 mW; 900 MHz; CAD optimization; CMOS RF power amplifier; balanced class-C amplifier; drain efficiency; integrated inductor model; n-well triple-metal digital process; on-chip matching network; parasitic-aware design; simulated annealing; spiral inductor; CMOS process; Computational modeling; Computer simulation; Design automation; Design optimization; Inductors; Network-on-a-chip; Power amplifiers; Radio frequency; Radiofrequency amplifiers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.902757

Filename

902757