Title :
A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers
Author :
Yan, William S T ; Luong, Howard C.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
fDate :
2/1/2001 12:00:00 AM
Abstract :
A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-μm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm2 and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively
Keywords :
CMOS analogue integrated circuits; cellular radio; frequency synthesizers; low-power electronics; radio receivers; 0.5 micron; 2 V; 34 mW; 900 MHz; GSM receiver; low power design; monolithic CMOS dual-loop frequency synthesizer; phase noise; spurious level; CMOS technology; Energy consumption; Frequency synthesizers; GSM; Low-noise amplifiers; Noise measurement; Phase measurement; Phase noise; Semiconductor device measurement; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
