Title :
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
Author :
Yang, Ching-Yuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
2/1/2001 12:00:00 AM
Abstract :
A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-μm n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the frequency of 120 MHz. The total power dissipation of the skew buffer is 218 mW for a 3 V supply. The core chip area is 980×1700 μm2
Keywords :
CMOS digital integrated circuits; buffer circuits; delay lock loops; high-speed integrated circuits; synchronisation; timing; 0.35 micron; 120 MHz; 218 mW; 3 V; bidirectional techniques; chip-to-chip system; clock-deskew buffer; coaxial cable; delay-locked loop; n-well CMOS process; one-wire approach; peak-to-peak jitter; skew-compensating clock distribution; CMOS process; Circuits; Clocks; Coaxial cables; Data processing; Delay; Frequency synchronization; Jitter; Power dissipation; Wires;
Journal_Title :
Solid-State Circuits, IEEE Journal of
