The twin-transistor noise-tolerant dynamic circuit technique

Author

Balamurugan, Ganesh ; Shanbhag, Naresh R.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

36

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

273

Lastpage

280

Abstract

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput

Keywords

CMOS logic circuits; crosstalk; high-speed integrated circuits; integrated circuit design; integrated circuit noise; logic design; low-power electronics; 0.35 micron; AND gate; CMOS technology; adder carry chain; circuit noise immunity; crosstalk noise problem; multiply-accumulate circuit; noise-tolerant dynamic circuit technique; noise-tolerant dynamic logic design; twin-transistor technique; voltage scaling; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Circuit synthesis; Crosstalk; Dynamic voltage scaling; Logic circuits; Logic design; Noise reduction;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.902768

Filename

902768