A 15-b pipelined CMOS floating-point A/D converter

Author

Thompson, Dwight U. ; Wooley, Bruce A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

36

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

299

Lastpage

303

Abstract

A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; floating point arithmetic; pipeline processing; switched capacitor networks; 0.5 micron; 15 bit; 380 mW; analog-to-digital converters; dynamic range extension; floating-point A/D converter; mantissa; peak SNR; peak signal-to-noise ratio; pipelined CMOS ADC; power dissipation; submicron CMOS technology; switched-capacitor type; three-stage pipelined VGA; variable gain amplifier; Analog-digital conversion; CMOS technology; Calibration; Dynamic range; Gain; Linearity; Power dissipation; Prototypes; Quantization; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.902771

Filename

902771