Title :
Correlated double sampling integrator insensitive to parasitic capacitance
Author :
Kajita, T. ; Temes, G.C. ; Moon, U.-K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fDate :
2/1/2001 12:00:00 AM
Abstract :
A new correlated double sampling (CDS) scheme is proposed which improves the operation of an integrator with a large parasitic capacitor at the input node of an op-amp. It suppresses the effects of the 1/f noise and offset voltage of the op-amp, as well as the kTC charge noise from the parasitic capacitor. It also reduces charge injection and clock feedthrough effects
Keywords :
1/f noise; analogue circuits; capacitance; integrating circuits; operational amplifiers; signal sampling; 1/f noise; charge injection reduction; clock feedthrough effects reduction; correlated double sampling integrator; kTC charge noise; offset voltage; op-amp; parasitic capacitance insensitive configuration; parasitic capacitor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010130
