DocumentCode
1438692
Title
A 15 MHz to 600 MHz, 20 mW, 0.38 mm 
Split-Control, Fast Coarse Locking Digital DLL in 0.13 
Author
Hoyos, Sebastian ; Tsang, Chi Wa ; Vanderhaegen, J. ; Yun Chiu ; Aibara, Y. ; Khorramabadi, H. ; Nikolic, B.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas AM Univ., College Station, TX, USA
Volume
20
Issue
3
fYear
2012
fDate
3/1/2012 12:00:00 AM
Firstpage
564
Lastpage
568
Abstract
A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.
Keywords
CMOS integrated circuits; analogue-digital conversion; clocks; delay lock loops; timing jitter; CMOS integrated circuit; binary search; delay locked loop; digital DLL; fast coarse locking; jitter performance; multiphase clock generation; pipelined analog-to-digital converters; power 20 mW; size 0.13 mum; time-interleaved analog-to-digital converters; two-stage digital split-control loop; CMOS integrated circuits; Clocks; Computer architecture; Delay; Delay lines; Jitter; Steady-state; All-digital delay-locked loop (DLL); DLL; split control loop;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2011.2106170
Filename
5704536
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