Self-aligned control of threshold voltages in sub-0.2-μm MOSFETs

Author

Kurata, Hajime ; Sugii, Toshihiro

Author_Institution

Fujitsu Labs. Ltd., Kanagawa, Japan

Volume

45

Issue

10

fYear

1998

fDate

10/1/1998 12:00:00 AM

Firstpage

2161

Lastpage

2166

Abstract

We propose a new method to control the threshold voltages (V_th) in sub-0.2 μm MOSFETs. The method suppresses V_th fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the V_th in numerous MOSFETs and show that our method can indeed suppress V_th fluctuations caused by variations in the fabricated gate length

Keywords

MOSFET; impurity distribution; ion implantation; semiconductor device models; 0.2 micron; MOSFET; channel impurity; device simulations; fabricated gate length; polysilicon gate formation; self-aligned control; threshold voltages; tilted ion implantation; two-dimensional process; Automatic control; Fabrication; Fluctuations; Impurities; Ion implantation; MOSFET circuits; Threshold voltage; Two dimensional displays; Ultra large scale integration; Voltage control;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.725250

Filename

725250