Improvement of the reliability of amorphous silicon transistors by conduction-band tail width reduction

We present theoretical and experimental evidence showing that bias induced threshold voltage degradation of a-Si:H transistors is reduced by decreasing the width of the conduction-band tail. We show that transistors which are made using a thick (0.5 μm) a-Si:H layer possess a narrower conduction-band tail compared to transistors made using thin (0.05 μm) a-Si:H layers. We find that bias-induced threshold voltage degradation decreases by a factor of two for thick-layered TFTs compared with conventional, thin-layered TFTs. Finally, we present device design guidelines for improving the reliability of a-Si:H TFTs including several possible device designs for achieving further improvements in the reliability of a-Si:H TFTs