Title :
An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor
Author :
Chen, Hsin-Li ; Wu, Ching-Yuan
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
10/1/1998 12:00:00 AM
Abstract :
An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFTs) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for a wide gate voltage range
Keywords :
MISFET; elemental semiconductors; grain size; semiconductor device models; silicon; thin film transistors; Si; analytical model; applied gate voltage; characterization; charge neutrality equation; grain-barrier height model; intrinsic poly-Si TFT; polysilicon TFT; quasi-two-dimensional method; thin-film transistor; Active matrix liquid crystal displays; Analytical models; Electrons; Equations; Grain boundaries; Grain size; Nonvolatile memory; Random access memory; Thin film transistors; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
